31 #ifndef _XTENSA_CORE_CONFIGURATION_H
32 #define _XTENSA_CORE_CONFIGURATION_H
49 #define XCHAL_HAVE_BE 0
50 #define XCHAL_HAVE_WINDOWED 0
51 #define XCHAL_NUM_AREGS 16
52 #define XCHAL_NUM_AREGS_LOG2 4
53 #define XCHAL_MAX_INSTRUCTION_SIZE 3
54 #define XCHAL_HAVE_DEBUG 1
55 #define XCHAL_HAVE_DENSITY 1
56 #define XCHAL_HAVE_LOOPS 0
57 #define XCHAL_HAVE_NSA 1
58 #define XCHAL_HAVE_MINMAX 0
59 #define XCHAL_HAVE_SEXT 0
60 #define XCHAL_HAVE_CLAMPS 0
61 #define XCHAL_HAVE_MUL16 1
62 #define XCHAL_HAVE_MUL32 1
63 #define XCHAL_HAVE_MUL32_HIGH 0
64 #define XCHAL_HAVE_DIV32 0
65 #define XCHAL_HAVE_L32R 1
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1
67 #define XCHAL_HAVE_CONST16 0
68 #define XCHAL_HAVE_ADDX 1
69 #define XCHAL_HAVE_WIDE_BRANCHES 0
70 #define XCHAL_HAVE_PREDICTED_BRANCHES 0
71 #define XCHAL_HAVE_CALL4AND12 0
72 #define XCHAL_HAVE_ABS 1
75 #define XCHAL_HAVE_RELEASE_SYNC 0
76 #define XCHAL_HAVE_S32C1I 0
77 #define XCHAL_HAVE_SPECULATION 0
78 #define XCHAL_HAVE_FULL_RESET 1
79 #define XCHAL_NUM_CONTEXTS 1
80 #define XCHAL_NUM_MISC_REGS 0
81 #define XCHAL_HAVE_TAP_MASTER 0
82 #define XCHAL_HAVE_PRID 1
83 #define XCHAL_HAVE_EXTERN_REGS 1
84 #define XCHAL_HAVE_MP_INTERRUPTS 0
85 #define XCHAL_HAVE_MP_RUNSTALL 0
86 #define XCHAL_HAVE_THREADPTR 0
87 #define XCHAL_HAVE_BOOLEANS 0
88 #define XCHAL_HAVE_CP 0
89 #define XCHAL_CP_MAXCFG 0
90 #define XCHAL_HAVE_MAC16 0
91 #define XCHAL_HAVE_VECTORFPU2005 0
92 #define XCHAL_HAVE_FP 0
93 #define XCHAL_HAVE_DFP 0
94 #define XCHAL_HAVE_DFP_accel 0
95 #define XCHAL_HAVE_VECTRA1 0
96 #define XCHAL_HAVE_VECTRALX 0
97 #define XCHAL_HAVE_HIFIPRO 0
98 #define XCHAL_HAVE_HIFI2 0
99 #define XCHAL_HAVE_CONNXD2 0
106 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 1
107 #define XCHAL_INST_FETCH_WIDTH 4
108 #define XCHAL_DATA_WIDTH 4
110 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1
111 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1
112 #define XCHAL_UNALIGNED_LOAD_HW 0
113 #define XCHAL_UNALIGNED_STORE_HW 0
115 #define XCHAL_SW_VERSION 800001
117 #define XCHAL_CORE_ID "lx106"
121 #define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6
126 #define XCHAL_HW_CONFIGID0 0xC28CDAFA
127 #define XCHAL_HW_CONFIGID1 0x1082B6F6
128 #define XCHAL_HW_VERSION_NAME "LX3.0.1"
129 #define XCHAL_HW_VERSION_MAJOR 2300
130 #define XCHAL_HW_VERSION_MINOR 1
131 #define XCHAL_HW_VERSION 230001
132 #define XCHAL_HW_REL_LX3 1
133 #define XCHAL_HW_REL_LX3_0 1
134 #define XCHAL_HW_REL_LX3_0_1 1
135 #define XCHAL_HW_CONFIGID_RELIABLE 1
137 #define XCHAL_HW_MIN_VERSION_MAJOR 2300
138 #define XCHAL_HW_MIN_VERSION_MINOR 1
139 #define XCHAL_HW_MIN_VERSION 230001
140 #define XCHAL_HW_MAX_VERSION_MAJOR 2300
141 #define XCHAL_HW_MAX_VERSION_MINOR 1
142 #define XCHAL_HW_MAX_VERSION 230001
149 #define XCHAL_ICACHE_LINESIZE 4
150 #define XCHAL_DCACHE_LINESIZE 4
151 #define XCHAL_ICACHE_LINEWIDTH 2
152 #define XCHAL_DCACHE_LINEWIDTH 2
154 #define XCHAL_ICACHE_SIZE 0
155 #define XCHAL_DCACHE_SIZE 0
157 #define XCHAL_DCACHE_IS_WRITEBACK 0
158 #define XCHAL_DCACHE_IS_COHERENT 0
160 #define XCHAL_HAVE_PREFETCH 0
170 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
176 #define XCHAL_HAVE_PIF 1
181 #define XCHAL_ICACHE_SETWIDTH 0
182 #define XCHAL_DCACHE_SETWIDTH 0
185 #define XCHAL_ICACHE_WAYS 1
186 #define XCHAL_DCACHE_WAYS 1
189 #define XCHAL_ICACHE_LINE_LOCKABLE 0
190 #define XCHAL_DCACHE_LINE_LOCKABLE 0
191 #define XCHAL_ICACHE_ECC_PARITY 0
192 #define XCHAL_DCACHE_ECC_PARITY 0
195 #define XCHAL_ICACHE_ACCESS_SIZE 1
196 #define XCHAL_DCACHE_ACCESS_SIZE 1
199 #define XCHAL_CA_BITS 4
206 #define XCHAL_NUM_INSTROM 1
207 #define XCHAL_NUM_INSTRAM 2
208 #define XCHAL_NUM_DATAROM 1
209 #define XCHAL_NUM_DATARAM 2
210 #define XCHAL_NUM_URAM 0
211 #define XCHAL_NUM_XLMI 1
214 #define XCHAL_INSTROM0_VADDR 0x40200000
215 #define XCHAL_INSTROM0_PADDR 0x40200000
216 #define XCHAL_INSTROM0_SIZE 1048576
217 #define XCHAL_INSTROM0_ECC_PARITY 0
220 #define XCHAL_INSTRAM0_VADDR 0x40000000
221 #define XCHAL_INSTRAM0_PADDR 0x40000000
222 #define XCHAL_INSTRAM0_SIZE 1048576
223 #define XCHAL_INSTRAM0_ECC_PARITY 0
226 #define XCHAL_INSTRAM1_VADDR 0x40100000
227 #define XCHAL_INSTRAM1_PADDR 0x40100000
228 #define XCHAL_INSTRAM1_SIZE 1048576
229 #define XCHAL_INSTRAM1_ECC_PARITY 0
232 #define XCHAL_DATAROM0_VADDR 0x3FF40000
233 #define XCHAL_DATAROM0_PADDR 0x3FF40000
234 #define XCHAL_DATAROM0_SIZE 262144
235 #define XCHAL_DATAROM0_ECC_PARITY 0
238 #define XCHAL_DATARAM0_VADDR 0x3FFC0000
239 #define XCHAL_DATARAM0_PADDR 0x3FFC0000
240 #define XCHAL_DATARAM0_SIZE 262144
241 #define XCHAL_DATARAM0_ECC_PARITY 0
244 #define XCHAL_DATARAM1_VADDR 0x3FF80000
245 #define XCHAL_DATARAM1_PADDR 0x3FF80000
246 #define XCHAL_DATARAM1_SIZE 262144
247 #define XCHAL_DATARAM1_ECC_PARITY 0
250 #define XCHAL_XLMI0_VADDR 0x3FF00000
251 #define XCHAL_XLMI0_PADDR 0x3FF00000
252 #define XCHAL_XLMI0_SIZE 262144
253 #define XCHAL_XLMI0_ECC_PARITY 0
260 #define XCHAL_HAVE_INTERRUPTS 1
261 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1
262 #define XCHAL_HAVE_NMI 1
263 #define XCHAL_HAVE_CCOUNT 1
264 #define XCHAL_NUM_TIMERS 1
265 #define XCHAL_NUM_INTERRUPTS 15
266 #define XCHAL_NUM_INTERRUPTS_LOG2 4
267 #define XCHAL_NUM_EXTINTERRUPTS 13
268 #define XCHAL_NUM_INTLEVELS 2
270 #define XCHAL_EXCM_LEVEL 1
274 #define XCHAL_INTLEVEL1_MASK 0x00003FFF
275 #define XCHAL_INTLEVEL2_MASK 0x00000000
276 #define XCHAL_INTLEVEL3_MASK 0x00004000
277 #define XCHAL_INTLEVEL4_MASK 0x00000000
278 #define XCHAL_INTLEVEL5_MASK 0x00000000
279 #define XCHAL_INTLEVEL6_MASK 0x00000000
280 #define XCHAL_INTLEVEL7_MASK 0x00000000
283 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00003FFF
284 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00003FFF
285 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00007FFF
286 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
287 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00007FFF
288 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00007FFF
289 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF
292 #define XCHAL_INT0_LEVEL 1
293 #define XCHAL_INT1_LEVEL 1
294 #define XCHAL_INT2_LEVEL 1
295 #define XCHAL_INT3_LEVEL 1
296 #define XCHAL_INT4_LEVEL 1
297 #define XCHAL_INT5_LEVEL 1
298 #define XCHAL_INT6_LEVEL 1
299 #define XCHAL_INT7_LEVEL 1
300 #define XCHAL_INT8_LEVEL 1
301 #define XCHAL_INT9_LEVEL 1
302 #define XCHAL_INT10_LEVEL 1
303 #define XCHAL_INT11_LEVEL 1
304 #define XCHAL_INT12_LEVEL 1
305 #define XCHAL_INT13_LEVEL 1
306 #define XCHAL_INT14_LEVEL 3
307 #define XCHAL_DEBUGLEVEL 2
308 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1
309 #define XCHAL_NMILEVEL 3
313 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
314 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
315 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
316 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
317 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
318 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
319 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
320 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
321 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
322 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
323 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
324 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_EDGE
325 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_EDGE
326 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_EDGE
327 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
330 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000
331 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
332 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00003F00
333 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000003F
334 #define XCHAL_INTTYPE_MASK_TIMER 0x00000040
335 #define XCHAL_INTTYPE_MASK_NMI 0x00004000
336 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
339 #define XCHAL_TIMER0_INTERRUPT 6
340 #define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED
341 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
342 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
343 #define XCHAL_NMI_INTERRUPT 14
346 #define XCHAL_INTLEVEL3_NUM 14
360 #define XCHAL_EXTINT0_NUM 0
361 #define XCHAL_EXTINT1_NUM 1
362 #define XCHAL_EXTINT2_NUM 2
363 #define XCHAL_EXTINT3_NUM 3
364 #define XCHAL_EXTINT4_NUM 4
365 #define XCHAL_EXTINT5_NUM 5
366 #define XCHAL_EXTINT6_NUM 8
367 #define XCHAL_EXTINT7_NUM 9
368 #define XCHAL_EXTINT8_NUM 10
369 #define XCHAL_EXTINT9_NUM 11
370 #define XCHAL_EXTINT10_NUM 12
371 #define XCHAL_EXTINT11_NUM 13
372 #define XCHAL_EXTINT12_NUM 14
379 #define XCHAL_XEA_VERSION 2
383 #define XCHAL_HAVE_XEA1 0
384 #define XCHAL_HAVE_XEA2 1
385 #define XCHAL_HAVE_XEAX 0
386 #define XCHAL_HAVE_EXCEPTIONS 1
387 #define XCHAL_HAVE_MEM_ECC_PARITY 0
388 #define XCHAL_HAVE_VECTOR_SELECT 1
389 #define XCHAL_HAVE_VECBASE 1
390 #define XCHAL_VECBASE_RESET_VADDR 0x40000000
391 #define XCHAL_VECBASE_RESET_PADDR 0x40000000
392 #define XCHAL_RESET_VECBASE_OVERLAP 0
394 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000
395 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000
396 #define XCHAL_RESET_VECTOR1_VADDR 0x40000080
397 #define XCHAL_RESET_VECTOR1_PADDR 0x40000080
398 #define XCHAL_RESET_VECTOR_VADDR 0x50000000
399 #define XCHAL_RESET_VECTOR_PADDR 0x50000000
400 #define XCHAL_USER_VECOFS 0x00000050
401 #define XCHAL_USER_VECTOR_VADDR 0x40000050
402 #define XCHAL_USER_VECTOR_PADDR 0x40000050
403 #define XCHAL_KERNEL_VECOFS 0x00000030
404 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000030
405 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000030
406 #define XCHAL_DOUBLEEXC_VECOFS 0x00000070
407 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x40000070
408 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x40000070
409 #define XCHAL_INTLEVEL2_VECOFS 0x00000010
410 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000010
411 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000010
412 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
413 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
414 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
415 #define XCHAL_NMI_VECOFS 0x00000020
416 #define XCHAL_NMI_VECTOR_VADDR 0x40000020
417 #define XCHAL_NMI_VECTOR_PADDR 0x40000020
418 #define XCHAL_INTLEVEL3_VECOFS XCHAL_NMI_VECOFS
419 #define XCHAL_INTLEVEL3_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
420 #define XCHAL_INTLEVEL3_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
427 #define XCHAL_HAVE_OCD 1
428 #define XCHAL_NUM_IBREAK 1
429 #define XCHAL_NUM_DBREAK 1
430 #define XCHAL_HAVE_OCD_DIR_ARRAY 0
439 #define XCHAL_HAVE_TLBS 1
440 #define XCHAL_HAVE_SPANNING_WAY 1
441 #define XCHAL_SPANNING_WAY 0
442 #define XCHAL_HAVE_IDENTITY_MAP 1
443 #define XCHAL_HAVE_CACHEATTR 0
444 #define XCHAL_HAVE_MIMIC_CACHEATTR 1
445 #define XCHAL_HAVE_XLT_CACHEATTR 0
446 #define XCHAL_HAVE_PTP_MMU 0
451 #define XCHAL_MMU_ASID_BITS 0
452 #define XCHAL_MMU_RINGS 1
453 #define XCHAL_MMU_RING_BITS 0