ESP8266
specreg.h
1 /*
2  * Xtensa Special Register symbolic names
3  */
4 
5 /* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */
6 
7 /* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1998-2002 Tensilica Inc.
8 
9  Permission is hereby granted, free of charge, to any person obtaining
10  a copy of this software and associated documentation files (the
11  "Software"), to deal in the Software without restriction, including
12  without limitation the rights to use, copy, modify, merge, publish,
13  distribute, sublicense, and/or sell copies of the Software, and to
14  permit persons to whom the Software is furnished to do so, subject to
15  the following conditions:
16 
17  The above copyright notice and this permission notice shall be included
18  in all copies or substantial portions of the Software.
19 
20  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
24  CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
27 
28 #ifndef XTENSA_SPECREG_H
29 #define XTENSA_SPECREG_H
30 
31 /* Include these special register bitfield definitions, for historical reasons: */
32 #include <xtensa/corebits.h>
33 
34 
35 /* Special registers: */
36 #define SAR 3
37 #define LITBASE 5
38 #define IBREAKENABLE 96
39 #define DDR 104
40 #define IBREAKA_0 128
41 #define DBREAKA_0 144
42 #define DBREAKC_0 160
43 #define EPC_1 177
44 #define EPC_2 178
45 #define EPC_3 179
46 #define DEPC 192
47 #define EPS_2 194
48 #define EPS_3 195
49 #define EXCSAVE_1 209
50 #define EXCSAVE_2 210
51 #define EXCSAVE_3 211
52 #define INTERRUPT 226
53 #define INTENABLE 228
54 #define PS 230
55 #define VECBASE 231
56 #define EXCCAUSE 232
57 #define DEBUGCAUSE 233
58 #define CCOUNT 234
59 #define PRID 235
60 #define ICOUNT 236
61 #define ICOUNTLEVEL 237
62 #define EXCVADDR 238
63 #define CCOMPARE_0 240
64 
65 /* Special cases (bases of special register series): */
66 #define IBREAKA 128
67 #define DBREAKA 144
68 #define DBREAKC 160
69 #define EPC 176
70 #define EPS 192
71 #define EXCSAVE 208
72 #define CCOMPARE 240
73 
74 /* Special names for read-only and write-only interrupt registers: */
75 #define INTREAD 226
76 #define INTSET 226
77 #define INTCLEAR 227
78 
79 #endif /* XTENSA_SPECREG_H */
80