ESP8266
corebits.h
1 /*
2  * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
3  *
4  * (In previous releases, these were defined in specreg.h, a generated file.
5  * This file is not generated, ie. it is processor configuration independent.)
6  */
7 
8 /* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/corebits.h#2 $ */
9 
10 /*
11  * Copyright (c) 2005-2007 Tensilica Inc.
12  *
13  * Permission is hereby granted, free of charge, to any person obtaining
14  * a copy of this software and associated documentation files (the
15  * "Software"), to deal in the Software without restriction, including
16  * without limitation the rights to use, copy, modify, merge, publish,
17  * distribute, sublicense, and/or sell copies of the Software, and to
18  * permit persons to whom the Software is furnished to do so, subject to
19  * the following conditions:
20  *
21  * The above copyright notice and this permission notice shall be included
22  * in all copies or substantial portions of the Software.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31  */
32 
33 #ifndef XTENSA_COREBITS_H
34 #define XTENSA_COREBITS_H
35 
36 /* EXCCAUSE register fields: */
37 #define EXCCAUSE_EXCCAUSE_SHIFT 0
38 #define EXCCAUSE_EXCCAUSE_MASK 0x3F
39 /* EXCCAUSE register values: */
40 /*
41  * General Exception Causes
42  * (values of EXCCAUSE special register set by general exceptions,
43  * which vector to the user, kernel, or double-exception vectors).
44  */
45 #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
46 #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
47 #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
48 # define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
49 #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
50 # define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
51 #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
52 # define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
53 #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
54 #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
55 #define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
56 #define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
57 #define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
58 /* Reserved 10..11 */
59 #define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
60 #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
61 #define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
62 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
63 #define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
64 #define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
65 #define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
66 /* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
67 #define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
68 /* Reserved 21..23 */
69 #define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
70 #define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
71 #define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
72 /* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
73 #define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
74 #define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
75 /* Reserved 30..31 */
76 #define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
77 #define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
78 #define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
79 #define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
80 #define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
81 #define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
82 #define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
83 #define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
84 #define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
85 /*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
86 /* Reserved 40..63 */
87 
88 /* PS register fields: */
89 #define PS_WOE_SHIFT 18
90 #define PS_WOE_MASK 0x00040000
91 #define PS_WOE PS_WOE_MASK
92 #define PS_CALLINC_SHIFT 16
93 #define PS_CALLINC_MASK 0x00030000
94 #define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
95 #define PS_OWB_SHIFT 8
96 #define PS_OWB_MASK 0x00000F00
97 #define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
98 #define PS_RING_SHIFT 6
99 #define PS_RING_MASK 0x000000C0
100 #define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
101 #define PS_UM_SHIFT 5
102 #define PS_UM_MASK 0x00000020
103 #define PS_UM PS_UM_MASK
104 #define PS_EXCM_SHIFT 4
105 #define PS_EXCM_MASK 0x00000010
106 #define PS_EXCM PS_EXCM_MASK
107 #define PS_INTLEVEL_SHIFT 0
108 #define PS_INTLEVEL_MASK 0x0000000F
109 #define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
110 /* Backward compatibility (deprecated): */
111 #define PS_PROGSTACK_SHIFT PS_UM_SHIFT
112 #define PS_PROGSTACK_MASK PS_UM_MASK
113 #define PS_PROG_SHIFT PS_UM_SHIFT
114 #define PS_PROG_MASK PS_UM_MASK
115 #define PS_PROG PS_UM
116 
117 /* DBREAKCn register fields: */
118 #define DBREAKC_MASK_SHIFT 0
119 #define DBREAKC_MASK_MASK 0x0000003F
120 #define DBREAKC_LOADBREAK_SHIFT 30
121 #define DBREAKC_LOADBREAK_MASK 0x40000000
122 #define DBREAKC_STOREBREAK_SHIFT 31
123 #define DBREAKC_STOREBREAK_MASK 0x80000000
124 
125 /* DEBUGCAUSE register fields: */
126 #define DEBUGCAUSE_DEBUGINT_SHIFT 5
127 #define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
128 #define DEBUGCAUSE_BREAKN_SHIFT 4
129 #define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
130 #define DEBUGCAUSE_BREAK_SHIFT 3
131 #define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
132 #define DEBUGCAUSE_DBREAK_SHIFT 2
133 #define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
134 #define DEBUGCAUSE_IBREAK_SHIFT 1
135 #define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
136 #define DEBUGCAUSE_ICOUNT_SHIFT 0
137 #define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
138 
139 /* MESR register fields: */
140 #define MESR_MEME 0x00000001 /* memory error */
141 #define MESR_MEME_SHIFT 0
142 #define MESR_DME 0x00000002 /* double memory error */
143 #define MESR_DME_SHIFT 1
144 #define MESR_RCE 0x00000010 /* recorded memory error */
145 #define MESR_RCE_SHIFT 4
146 #define MESR_LCE
147 #define MESR_LCE_SHIFT ?
148 #define MESR_LCE_L
149 #define MESR_ERRENAB 0x00000100
150 #define MESR_ERRENAB_SHIFT 8
151 #define MESR_ERRTEST 0x00000200
152 #define MESR_ERRTEST_SHIFT 9
153 #define MESR_DATEXC 0x00000400
154 #define MESR_DATEXC_SHIFT 10
155 #define MESR_INSEXC 0x00000800
156 #define MESR_INSEXC_SHIFT 11
157 #define MESR_WAYNUM_SHIFT 16
158 #define MESR_ACCTYPE_SHIFT 20
159 #define MESR_MEMTYPE_SHIFT 24
160 #define MESR_ERRTYPE_SHIFT 30
161 
162 
163 #endif /*XTENSA_COREBITS_H*/
164 
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